The process of material removal from the surface of a pattern structure (such as a semiconductor wafer) might lead to such undesirable effects as residue, dishing, erosion and corrosion. Timely detection of these effects can be used for controlling the material removal process.
In the manufacture of semiconductor devices, aluminum has been used almost exclusively as the main material for interconnects. However, recent developments in this field of the art have shown that copper is posed to take over as the main on-chip conductor for all types of integrated circuits. Compared to aluminum, copper has a lower resistance, namely less than 2 μΩ-cm even when deposited in narrow trenches, versus more than 3 μΩ-cm for aluminum alloys. This lower resistance is critically important in high-performance microprocessors and fast static RAMs, since it enables signals to move faster by reducing the so-called “Resistance-Capacitance” (RC) time delay. Additionally, copper has a superior resistance to electromigration, which leads to lower manufacturing costs as compared to aluminum-based structures.
During the manufacture of semiconductor devices, a wafer undergoes a sequence of photolithography-etching steps to produce a plurality of patterned layers (stacks). Then, depending on the specific layers or production process, the uppermost layer of the wafer may or may not undergo a CMP process to provide a smooth surface of this layer. This is true for the copper-based or tungsten-based structures, and also for the aluminum-based semiconductor structures in which aluminum has been deposited by the dual Damascene process.
Copper has properties that add to the polishing difficulties. Unlike tungsten, copper is a soft metal and subject to scratching and embedding particles during polishing. Additionally, owing to the fact that copper is highly electrochemically active and does not form a natural protective oxide, it corrodes easily. With conventional technology of planarization, ILD polishing occurs after every metal deposition and etch step. The same is not true for damascene processing, wherein the post-polish surface is, expected to be free of topography. However, topography is induced because of erosion of densely packed small feature arrays and dishing of the metal surface in large features.
Copper CMP is more complex because of the need to completely remove the tantalum or tantalum nitride barrier layers and copper uniformity without the overpolishing of any feature. This is difficult because current copper deposition processes are not as uniform as the oxide deposition process. Additionally, tolerances for erosion and dishing are much narrower for copper CMP.
The effects of residues, dishing and erosion present defects on the wafer induced by the CMP process applied thereto. Dishing and erosion may deteriorate the interconnections' quality, especially when the copper thickness is reduced. Indeed, the reduction of the copper thickness results in the increase of RC constants, resulting in the slower functioning of the integrated circuit. As indicated above, the lower resistance is critically important in high-performance microprocessors and fast static RAMs. The ability to monitor the level of residues, dishing and erosion can enable tighter control of the CMP process.
CMP of dielectric layers can also lead to the pattern dependent non-planarity effects, such as erosion and dishing. An example of the dielectric CMP is the shallow trench isolation (STI) process, which forms silicon dioxide isolation channels surrounding the silicon nitride covered active transistor areas. Here, the surface non-planarity is caused owing to the fact that different dielectric materials of the structure exposed to the polish process are removed with different rates. Silicon dioxide areas typically undergo enhanced removal relative to the adjacent silicon nitride areas. In large silicon dioxide features, this results in dishing; in densely patterned areas, the CMP process can erode both the silicon nitride and silicon dioxide features. Over-polishing usually results in an increased dishing, while under-polishing results in residues over the silicon nitride areas.